Current CMOS technology uses silicides as contacts to the source/drain (S/D) regions of the devices that are fabricated upon a Si-containing substrate. Examples of silicides with low resistivity and contact resistance that are currently being used as S/D contacts are the C54 phase of TiSi2, CoSi2, and NiSi. All three of these silicides are integrated using a self-aligned silicide process (i.e., a salicide process). This process consists of a blanket deposition of the metal (Ti, Co, or Ni) with a cap layer (such as TiN, Ti or W), annealing at a first lower temperature to form a first silicide phase (i.e., the C49 phase of TiSi, CoSi, or NiSi), selectively wet etching the cap layer and unreacted metal that is not in contact with silicon, and annealing at a second higher temperature to form the low resistance metal silicide phase (the C54 phase of TiSi2 or CoSi2). For the low resistance NiSi, the second anneal is typically not needed.
The advantage of these particular silicides is that they all may be implemented with the self-aligned process avoiding additional lithographic steps. One advantage of Ni silicides is that Ni monosilicide contacts are thinner than conventional Ti or Co silicide contacts. A disadvantage of Ni silicide contacts is that the higher resistivity nickel disilicide phase is produced during high temperature processing steps, rather than the preferred lower resistivity nickel monosilicide, NiSi, phase. The formation of the nickel disilicide phase is nucleation controlled. A disadvantage of forming nickel disilicides is that it consumes twice the amount of Si than the preferred NiSi phase. Moreover, nickel disilicides produce a rougher silicide/Si wafer interface and also have a higher sheet resistivity than the preferred NiSi.
Another disadvantage of NiSi contacts is that they tend to agglomerate readily at standard CMOS processing temperatures. The term “agglomerate” is used herein to denote that a very thin film of NiSi tends to gather into a mass or cluster at temperatures on the order of about 400° C. or higher. The agglomeration problem is not limited to Ni silicides. It typically occurs for various thin films other than NiSi and is worst for low melting point materials. Pt silicide is one example of another silicide that tends to agglomerate readily.
Preventing agglomeration is a key to getting the NiSi process to yield adequately. Attempts have been made in the prior art to develop methods for preventing the agglomeration of NiSi. Most of these prior art approaches use a binary or ternary Ni alloy. The alloy may be contained within the metal layer itself, or it can be formed atop the metal layer such that during annealing diffusion and intermixing of alloy, metal and Si occurs. These alloys, however, require much addition work to define the alloy concentrations and to develop adequate post silicide formation etches.
In addition to the use of Ni alloys, there have been some fairly recent publications that have shown that BF2 implants to form pFET regions can enhance NiSi formation compared with the nFET regions in which BF2 was not implanted. See, for example, A. S. Wong, et al., Appl. Phys. Lett. 81, 5138(2002); S. K. Donthu, et al., Mater. Res. Soc. Symp. Proc. 716, 465 (2002); and C. Lavoie, et al., Microelectronic Engineering 70 (2003) 144–157. While these three publications show an improvement in the NiSi in BF2 implanted regions they do not disclose the purposeful implantation of F or other like ions into both n and p regions to stabilize NiSi formation and prevent agglomeration of NiSi. Implantation of BF2 requires activation anneal for the B. Moreover, BF2 implantation does not fix the agglomeration problem on nFETs.
In view of the above, there is a need for providing a new and improved method to fabricate metal silicide films, e.g., NiSi films, that show little or no agglomeration upon further heat treatments.